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Principal Design Engineer
Location:
Santa Clara, CA
Description:
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. We develop the architecture, IP development, SOC , create the physical design, and work with the world's leading data center and enterprise companies to bring next generation networking to reality. What You Can Expect Lead the SOC Design or Own a significant section of our Switch design IPs Work closely with Architects and define IP micro-architecture and SOC architecture and drive to Tapeout Drive Power Saving innovation. Review , evaluate 3rd party IP Work with DFT team to integrate test features Work with DV team to ensure feature coverage and debugging support physical design team for timing analysis/timing closure. What We're Looking For Experience level: 12+ years' of relevant industry experience. Master's degree in Computer Science, Electrical Engineering or related fields with 10 years of experience. Industry experience: Experience with digital design microarchitecture development is a must. Design/RTL experience in Verilog or SV is a must. Experience with logic synthesis, synthesis constraint development and backend flow and static timing analysis. Knowledge of scripting languages, such as PERL, Python Added advantage: Experience with Ethernet switch design. Ethernet protocols (IEEE 802.3, 802.1Q, 802.1D, Routing protocols) Digital power estimation and optimization General : Good learning , problem solving interpersonal and communication skills. Ability to be a part of a team, working in cooperation. Self-motivated team player able to thrive in a fast-paced engineering environment Expected Base Pay Range (USD) 160,200 - 240,000, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at XXXX@marvell.com.
Company:
Marvell Semiconductor
Posted:
June 19 on TopUSAJobs
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