This listing was posted on ITJobsWeb.
Design Verification Engineer, Multimedia, Silicon
Location:
Mountain View, CA
Description:
About the job Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.The US base salary range for this full-time position is $150,000-$223,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Preferred qualifications: Experience with image processing or other multimedia IPs such as display or video codec. Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture. Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification. Experience with emulation platforms. Responsibilities Plan the verification of complex multimedia digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using System Verilog and UVM. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Requisition #: 116637390298063558pca3lyuhf
Company:
Google
Posted:
June 22 on ITJobsWeb
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